1. Field of the Invention
The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly to a semiconductor device in which a single-crystalline semiconductor film continuously formed on both the surface of a single-crystalline semiconductor substrate and an insulating film coating the substrate is constructed to have a lower resistance region, and a method of fabricating the semiconductor device by making use of the single-crystallization of a polycrystal through the irradiation with a laser beam.
2. Description of the Prior Art
FIG. 1(a) shows the cross-sectional construction of an insulated gate type FET (i.e., MOSFET) according to the prior art. The N-channel MOSFET according to the prior art is so constructed that N-type regions 12 and 13 acting as a source and a drain, respectively, are formed in a P-type substrate 11 and that a gate electrode 15 is attached to a gate insulating film 14. Incidentally, reference numeral 16 indicates an insulating film for inter-element isolation, which is selectively formed. According to this element construction, source and drain electrodes 17 and 18 have to be led out through holes (i.e., contact holes) which are smaller than the source and drain diffusion regions 12 and 13. As a result, the source and drain diffusion regions are made the same or larger than the contact holes, so that the parasitic capacitances C.sub.DS and C.sub.SS between those diffusion regions and the substrate 11 cannot be ignored. FIG. 1(b) shows an equivalent circuit of the MOSFET having the parasitic capacitances C.sub.DS and C.sub.SS. A MOSFET 101 cannot realize a higher speed operation unless the parasitic capacitance C.sub.DS is reduced because the operating speed of the element is determined by the charging and discharging periods of the capacitance C.sub.DS and the capacitance of the next stage gate.
On the other hand, the leak currents between the source and drain diffusion regions and the substrate cannot be ignored, and the conventional MOSFET shown in FIG. 1 has a problem even in a low power consumption operation.
The drawback thus far described is substantially similarly experienced in other FET's than the MOSFET, i.e., a Schottky's barrier gate FET (i.e., SB FET) or a junction gate FET (i.e., J FET).
On the other hand, a bipolar transistor has many problems to be solved, e.g., the problem that the high-frequency characteristics are deteriorated due to the parasitic capacitance to be established between the base and the collector thereof.